1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a gate electrode of an insulated gate transistor and an electrode of a capacitor.
2. Description of the Background Art
In an insulated gate transistor according to the prior art, so-called scaling has been performed in which an operating supply voltage is set low from the viewpoint of hot-carrier resistance and reliability of a gate insulation film along with a finer structure of an element.
In a short channel transistor having a small channel length, a saturation current IDsat is generally proportional to a difference (VGxe2x88x92Vth) between a gate voltage VG and a threshold voltage Vth. For this reason, if the gate voltage VG is equal to a supply voltage VDD, the saturation current IDsat is proportional to a difference (VDDxe2x88x92Vth) between the supply voltage and the threshold voltage.
In order to suppress a short circuit current of a circuit and surely turn off a transistor, a current flowing between a gate and a source when the gate voltage VG is equal to or smaller than the threshold voltage, that is, a subthreshold current should be suppressed.
A current flowing when the gate voltage is 0V, that is, an OFF-state current IOFF is calculated by Equation 1, wherein a gate voltage VG necessary for increasing the subthreshold current by one digit, that is, a subthreshold coefficient is represented by S and a threshold voltage Vth is set to VG applied when a drain current ID for 1.0 xcexcm of a gate width W is equal to 0.1 xcexcA:
The subthreshold coefficient S is physically calculated by Equation 2:
IOFF=0.1 xcexcAxc3x9710xe2x88x92(Vth/S)xe2x80x83xe2x80x83(1)
                    S        =                              kT            q                    xc3x97                      log            e                    ⁢          10          xc3x97                      (                          1              +                                                CB                  +                  Cit                                COX                                      )                                              (        2        )            
wherein k represents a Boltzmann""s constant, q represents an elementary charge, e represents a base of a natural logarithm, T represents an absolute temperature, CB represents a depletion layer capacitance between a channel and a substrate, Cit represents a capacitance based on an interface state of a gate oxide film, and COX represents a capacitance of the gate oxide film.
If CB and Cit are equal to 0, S=60 mV/decade is obtained at a room temperature of 300 K. If CB and Cit are not equal to 0, S=70 to 100 mV/decade is obtained. For example, when an OFF-state current IOFF for a gate width of 1.0 xcexcm in a general transistor is set to 0.1 pA and a subthreshold coefficient S is set to 85 mV/decade, Vth is set to 0.51V by Equation 3 when a drain voltage VD is a supply voltage VDD. This value is not varied when a standard of the OFF-state current IOFF and a value of the subthreshold coefficient S are not changed even if the supply voltage VDD is reduced.                     Vth        =                  S          xc3x97                      log            e                    ⁢                      xe2x80x83                    ⁢                                    0.1              ⁢              μ              ⁢                              xe2x80x83                            ⁢              A                                      0.1              ⁢              p              ⁢                              xe2x80x83                            ⁢              A                                                          (        3        )            
Accordingly, even if the supply voltage VDD is set low when making a finer structure, the threshold voltage Vth is not subjected to the scaling because the OFF-state current IOFF is restricted. On the other hand, the saturation current IDsat is proportional to (VDDxe2x88x92Vth). Therefore, current driving force is reduced and an operating speed of an element is decreased in some cases when making a finer structure.
In a transistor having a low threshold voltage Vth, an impurity concentration of a channel is low after making a finer structure. For this reason, punch-through is caused so that a current which cannot be controlled by the gate voltage VG flows. Consequently, a circuit performs wrong operation.
In the case where a transistor is used for an output stage of the circuit or the like, a supply voltage VDD1 applied to the transistor is sometimes set higher than a supply voltage VDD of other circuit portions. In the same transistor, for example, a voltage of 0 V to VDD is applied as a gate voltage VG and a voltage of 0 V to VDD1 is applied as a drain voltage VD. In this case, a maximum voltage applied to a gate insulation film is VDD1 if the gate voltage VG is 0 V and the drain voltage VD is VDD1. In such a transistor, therefore, a thickness of the gate insulation film should be resistant to an electric field having an intensity obtained by VDD1/tOX.
The foregoing will further be described with reference to FIGS. 72 to 74. In FIG. 72, a P-channel MOS transistor M1 and an N-channel MOS transistor M2 form an inverter. An input voltage VIN applied to an input terminal of the inverter has a value of 0 V or 2.5 V. A voltage of 5 V is applied to a source of the transistor M1, and a ground voltage VSS (0 V) is applied to a source of the transistor M2. With such a structure, an output voltage VOUT is 5 V when the input voltage VIN is 0 V, and a maximum voltage (5 V) is applied between a drain and a gate of the transistor M2. At this time, the maximum voltage (5 V) is also applied between a drain and a gate of the transistor M1.
In FIG. 73, P-channel MOS transistors M3 and M5 and N-channel MOS transistors M4 and M6 form an OR circuit. The transistors M4 and M6 are connected in parallel. Parallel connected elements comprising the transistors M4 and M6, and the transistors M3 and M5 are connected in series. A supply voltage VDD is given to a source of the transistor M5. A connecting point of drains of the parallel connected elements and the transistor M3 acts as an output terminal. An input voltage VIN1 given to gates of the transistors M3 and M4 and an input voltage VIN2 given to gates of the transistors M5 and M6 are changed together within a range of 0 V to 2.5 V. For this reason, a maximum voltage (5 V) is applied between gates and drains of the transistors M4 and M6 if the input voltages VIN1 and VIN2 are 0 V, and the maximum voltage (5 V) is applied between the gate and source of the transistor M5 if the input voltage VIN2 is 0 V, for example.
In FIG. 74, P-channel MOS transistors M7 and M9 and N-channel MOS transistors M8 and M10 form a NAND circuit. The transistors M7 and M9 are connected in parallel. Parallel connected elements comprising the transistors M7 and M9, and the transistors M8 and M10 are connected in series. A supply voltage VDD is given to sources of the transistors M7 and M9. Drains of the transistors M7 and M9 are connected to an output terminal. A drain of the transistor M8 is also connected to the same output terminal. A ground voltage VSS (0 V) is given to a source of the transistor M10. An input voltage VIN1 given to gates of the transistors M7 and M8 and an input voltage VIN2 given to gates of the transistors M9 and M10 are changed together within a range of 0 V to 2.5 V. For this reason, a maximum voltage (5 V) is applied between the gate and drain of the transistor M8 and the maximum voltage is also applied between the gates and drains of the transistors M7 and M9 if either of the input voltages VIN1 and VIN2 is 0 V, for example.
FIG. 75 typically shows a section of a main part of the insulated gate transistor according to the prior art. In the case where the transistor shown in FIG. 75 is an N-channel MOS transistor, the reference numeral 1 denotes a P type silicon substrate having a resistivity of several xcexa9xc2x7cms to several tens xcexa9xc2x7cms and a crystallographic axis  less than 100 greater than , the reference numeral 2 denotes a P well formed in the vicinity of a surface of the silicon substrate 1, the reference numeral 3 denotes a channel dope region which is formed in the P well 2 and serves to control a threshold and to prevent punch-through, the reference numeral 4 denotes a gate insulation film formed on one of principal planes of the silicon substrate 1 by using a silicon oxide film as a material, the reference numeral 5 denotes a gate electrode formed on the gate insulation film 4 by using, as a material, a polycrystalline silicon film doped with phosphorus having a high concentration, the reference numeral 6 denotes a drain region which is formed on one of principal planes of the P well 2 and includes a drain region 61 having a high impurity concentration and a drain region 62 having a low impurity concentration, the reference numeral 7 denotes a source region which is formed on one of the principal planes of the P well 2 and includes a source region 71 having a high impurity concentration and a source region 72 having a low impurity concentration, the reference numeral 8 denotes a P type substrate electrode having a high impurity concentration for giving an electric potential of the silicon substrate 1 or the P well 2 from one of the principal planes of the silicon substrate 1, the reference numeral 9 denotes an isolation film for isolating the insulated gate transistor shown in the drawing from other components such as the substrate electrode 8 and the like, the reference numeral 10 denotes a region provided in the vicinity of the gate electrode 5, whose conductivity type is inverted to form a channel when a positive voltage is applied to the gate electrode 5, and the reference numeral 11 denotes a sidewall which is provided on a side of the gate electrode 5 and is usually formed of a silicon oxide film or a silicon nitride film.
FIGS. 76 and 77 are typical enlarged views showing a section of a main part of a structure of the silicon substrate 1 provided in the vicinity of the gate insulation film 4 in FIG. 75 according to examples which are different from each other. The channel dope region 3 is formed by only a P type semiconductor region 3p as shown in FIG. 76 or is formed by an N type semiconductor region 3n and the P type semiconductor region 3p as shown in FIG. 77.
When a transistor shown in FIG. 77 is turned on, a channel is formed under the semiconductor region 3n. 
FIG. 78 typically shows a section of a main part of an N-channel MOS transistor which operates with a high voltage and is one of vertical type power MOS transistors according to the prior art. In FIG. 78, the reference numeral 1A denotes a silicon substrate, the reference numeral 3A denotes a channel dope region which is formed on one of principal planes of the silicon substrate 1A and serves to control a threshold and to prevent punch-through, the reference numeral 4A denotes a gate insulation film formed on sides of a plurality of trenches extending perpendicularly to the drawing by using a silicon oxide film as a material, the reference numeral 5A denotes a gate electrode provided so as to fill up the trenches on which the gate insulation film 4A is formed, the reference numeral 61A denotes a drain region formed by doping the other principal plane of the silicon substrate 1A with an N type impurity having a high concentration, the reference numeral 62A denotes a drain region doped with the N type impurity having a comparatively lower concentration than that of the drain region 61A having a high impurity concentration in contact therewith, the reference numeral 71A denotes a source region formed in contact with the gate insulation film 4A by doping one of the principal planes of the silicon substrate 1A with the N type impurity having a high concentration, the reference numeral 8A denotes a P type substrate electrode having a high impurity concentration which is provided to give an electric potential of the silicon substrate 1A or a P well 2A from one of the principal planes of the silicon substrate 1A, the reference numeral 10A denotes a region provided in the vicinity of the gate electrode 5A, whose conductivity type is inverted to form a channel when a positive voltage is applied to the gate electrode 5A, and the reference numeral 11A denotes a sidewall which is provided on both sides of the gate electrode 5A on the silicon substrate 1A and is usually formed of a silicon oxide film or a silicon nitride film.
FIG. 79 is a graph showing a relationship between a gate voltage and a source-drain current which is obtained when a source has a voltage of 0 V, an optional positive voltage is given to a drain and a substrate has a voltage of 0 V or an optional negative voltage in the MOS transistor shown in FIG. 75 or 78. In FIG. 79, a one-dotted chain line indicates a case where the gate insulation films 4 and 4A are thin, for example, have a thickness of 8 nm, and a broken line indicates a case where structures of portions other than the gate insulation films 4 and 4A are identical and only the gate insulation films 4 and 4A are thick, for example, have a thickness of 20 nm. It is apparent from FIG. 79 that a gate-source voltage for turning on/off the insulated gate transistor, that is, a threshold voltage is raised if the thickness of the gate insulation film is increased, and is lowered if the same thickness is reduced.
When the transistor is brought into an ON state and is in an OFF state, the thickness of the gate insulation film is constant. Therefore, a subthreshold coefficient S which is an inverse number of each of maximum gradients S1 and S2 of a curve in FIG. 79 physically satisfies Equation 4, and the maximum gradients S1 and S2 are not changed. In the Equation 4, k represents a Boltzmann""s constant, T represents an absolute temperature, and q represents an elementary charge.                     S         greater than                               kT            q                    xc3x97                      log            e                    ⁢          10                                    (        4        )            
FIG. 80 shows a relationship between a gate voltage and a gate-drain capacitance CGD and a gate-source capacitance CGS, and a relationship between the gate voltage and a gate-substrate capacitance CGB in the MOS transistor in FIG. 75 or 78.
The gate capacitance will be described below. The gate capacitance includes the gate-drain capacitance CGD, the gate-source capacitance CGS and the gate-substrate capacitance CGB. In general, the gate-drain capacitance CGD is a sum of a fringing capacitance generated on a gate electrode side and an overlap capacitance of a portion in which the gate overlaps with the drain if the gate voltage VG is smaller than the threshold voltage Vth, and is equal to an oxide film capacitance COX if the gate voltage VG is greater than the threshold voltage Vth.
The gate-source capacitance CGS is a sum of the fringing capacitance and the overlap capacitance within a total gate voltage range.
The gate-substrate capacitance CGB is equal to a value obtained by subtracting an overlap capacitance COV from the oxide film capacitance COX within a range in which the channel is accumulated, that is, the gate voltage VG is smaller than a flat band voltage VFB, and is almost obtained by (COXxe2x88x92COV)xc3x97CB/(COX+CB) if VFB less than VG less than Vth and is set to 0 if VG greater than Vth.
It is apparent from FIG. 80 that the gate capacitance is coincident with the oxide film capacitance COX when the transistor is in a stable state apart from a transition region in which an on-off state thereof is switched.
In the insulated gate transistor according to the prior art described above, a polycrystalline silicon having a low resistivity and a high concentration is used for the gate electrode 5. In the insulated gate transistor according to the prior art, furthermore, a silicon oxide film having a small interface statexc2x7trap density is mainly used as the gate insulation film. Thus, the insulated gate transistor has had high reliability.
Japanese Patent Laid-Open Gazettes 3-293767, 57-54372 and 54-87192 have described examples in which a conductivity type of a gate electrode is different from that of a source-drain region and the gate electrode has a high concentration.
Japanese Patent Laid-Open Gazettes 7-273212 and 7-321220 have described examples in which the structures disclosed in the above-mentioned publications are applied to a transistor having a buried channel.
In addition, Japanese Patent Laid-Open Gazette 6-61437 has described an example in which a ferroelectric film is used for a gate insulation film having the structures disclosed in the above-mentioned publications.
Japanese Patent Laid-Open Gazettes 5-235335 and 7-202178 have described examples in which a material having a small bandgap is used for a gate electrode.
Japanese Patent Laid-Open Gazette 60-32354 has described an example in which a part of a gate electrode has a low resistance.
The insulated gate transistor according to the prior art has the above-mentioned structures. The subthreshold coefficient S is greater than 60 mV/decade at a room temperature during on/off. Therefore, even if the supply voltage is reduced by the scaling, the threshold voltage is not subjected to the scaling when the OFF-state current is kept constant. Consequently, the current driving force is reduced.
Conversely, if the threshold voltage is subjected to the scaling, the OFF-state current is increased. Consequently, a logical amplitude is reduced, dissipation power is increased, and a current consumed on standby, that is, a standby current is increased and a storage capability is lowered when the transistor is used for a DRAM or the like.
In a power element shown in FIG. 78, for example, a capacitance obtained in a state in which a gate is off, that is, an overlap capacitance and a gate-substrate capacitance are increased. In addition, a supply voltage is higher than a gate voltage in the power element. Therefore, an amplification factor is great, and a gate capacitance acting as a Miller capacitance is very increased. Thus, in the case where the gate capacitance is great, a switching speed is decreased so that a switching loss is increased.
Furthermore, in the case where a plurality of circuits having various supply voltages are provided on one chip, the supply voltage is sometimes set higher than the supply voltages of other circuit portions. Depending on the transistor, a voltage which is higher than voltages of the other circuit portions is applied to the gate insulation film. As a result, the gate insulation film of the transistor in an output stage should be resistant to a voltage which is higher than voltages of the transistors in the other circuit portions, for example. Therefore, a thickness of the gate insulation film should be increased. An operating speed is decreased due to a reduction in the current driving force, and an efficiency of applying a gate electric field to a channel is reduced so that punch-through is caused.
A first aspect of the present invention is directed to a semiconductor device comprising a gate electrode provided opposite to a first semiconductor region where a channel is to be formed with a gate insulation film interposed therebetween, the gate electrode including a second semiconductor region which is provided in contact with the gate insulation film, wherein a depletion layer is generated in the second semiconductor region if the channel is insulating, and a width of the depletion layer is smaller than in the case where the channel is insulating or the depletion layer disappears if the channel is conducting.
A second aspect of the present invention is directed to the semiconductor device according to the first aspect of the present invention, wherein the second semiconductor region has a conductivity type which is reverse to a conductivity type of a source region or a drain region provided in contact with the first semiconductor region.
A third aspect of the present invention is directed to the semiconductor device according to the first aspect of the present invention, wherein the gate electrode has a resistance layer having a resistance value which is lower than a resistance value of the second semiconductor region, which the resistance layer is apart from an area of the gate insulation film, under which the area the channel is to be conducting.
A fourth aspect of the present invention is directed to the semiconductor device according to the third aspect of the present invention, wherein an impurity concentration of the second semiconductor region is locally enriched at an end of the second semiconductor region which is close to the drain region.
A fifth aspect of the present invention is directed to a semiconductor device comprising a gate electrode provided opposite to a first semiconductor region where a channel is to be formed with a gate insulation film interposed therebetween, the gate electrode including a second semiconductor region which is provided in contact with the gate insulation film, wherein a depletion layer is generated in the second semiconductor region if the channel is conducting, and a width of the depletion layer is smaller than in the case where the channel is conducting or the depletion layer disappears if the channel is insulating, and the depletion layer is formed on a condition that a maximum voltage to be supplied to the semiconductor device is applied between the gate electrode and a source/drain electrode of the semiconductor device.
A sixth aspect of the present invention is directed to the semiconductor device according to the first aspect of the present invention, wherein the first semiconductor region is formed in a semiconductor layer provided on an insulator.
A seventh aspect of the present invention is directed to a semiconductor device, comprising a first gate electrode having a first plane provided opposite to a first semiconductor region where a channel is to be formed with a first gate insulation film interposed therebetween, a second gate insulation film formed on a second plane of the first gate electrode which is provided opposite to the first plane, and a second gate electrode which is provided opposite to the first gate electrode through the second gate insulation film, wherein the second gate electrode has a second semiconductor region provided in contact with the second gate insulation film, a depletion layer is generated in the second semiconductor region if a first voltage is applied, and a width of the depletion layer is smaller than in the case where the first voltage is applied or the depletion layer disappears if a second voltage is applied, and the second voltage causes a more current to flow through the channel than the first voltage.
An eighth aspect of the present invention is directed to the semiconductor device according to any of the first to seventh aspects of the present invention, wherein the gate electrode includes a ferroelectric.
A ninth aspect of the present invention is directed to a semiconductor device comprising a dielectric film having first and second principal planes, a first electrode provided on the first principal plane and formed of a semiconductor having a first conductivity type, and a second electrode provided on the second principal plane and formed of a semiconductor having a second conductivity type which is reverse to the first conductivity type, wherein the first and second electrodes have greater widths of depletion layers when a voltage making a P type semiconductor a positive potential and making an N type semiconductor a negative potential is not applied than when the voltage is applied.
A tenth aspect of the present invention is directed to the semiconductor device according to the eighth aspect of the present invention, wherein the dielectric film includes a ferroelectric.
According to the first aspect of the present invention, a virtual thickness of the gate insulation film can be varied with a change of the depletion layer formed on the gate electrode, and breakdown voltages of the channel and the gate insulation film of an insulated gate transistor can be controlled. Consequently, a characteristic of the transistor can be enhanced.
According to the second aspect of the present invention, a more current is caused to flow through the channel when the second voltage is applied to the first semiconductor region than when the first voltage is applied to the first semiconductor region. In other words, the width of the depletion layer is smaller in an ON state of the transistor than in an OFF state thereof, or is zero. Therefore, high current driving force can be obtained and a switching loss can be reduced.
According to the third aspect of the present invention, it is possible to reduce the resistance value of the gate electrode whose resistance is comparatively increased with a reduction in the impurity concentration caused by formation of the depletion layer. Thus, an operating speed can be prevented from being decreased.
According to the fourth aspect of the present invention, the portion of the gate electrode which is close to the drain region is depleted with difficulty due to existence of the resistance layer. The current driving force can be prevented from being lowered due to the depletion layer generated in the drain region when the transistor is turned on.
According to the fifth aspect of the present invention, an effective thickness of the gate insulation film is increased with a maximum voltage by the generated depletion layer so that a breakdown voltage of the gate insulation film of the transistor can be enhanced.
According to the sixth aspect of the present invention, the channel is formed on an epitaxial layer formed on the insulator. Therefore, effects of depletion of the gate electrode can be increased more than in the case where a whole substrate is formed of a semiconductor.
According to the seventh aspect of the present invention, a virtual thickness of the second gate insulation film can be varied with a change of the depletion layer formed on the second gate electrode, and breakdown voltages of the channel and the second gate insulation film of the insulated gate transistor can be controlled. Consequently, a characteristic of the transistor can be enhanced.
According to the eighth aspect of the present invention, the gate insulation film itself spontaneously polarizes by charges generated on the gate insulation film by a dielectric. Consequently, a threshold voltage can be increased when the insulated gate transistor is brought from an ON state into an OFF state, and a lower leak current can be obtained. By the spontaneous polarization of the gate insulation film, the threshold voltage can be reduced when the insulated gate transistor is brought from the OFF state into the ON state.
According to the ninth aspect of the present invention, a capacitance can be varied by the depletion layer and an effective thickness of the dielectric film can be changed. For example, in the case where the semiconductor device is used for a memory cell, a refresh interval can be increased and a capacitance of a cell which is not accessed is reduced so that a writing speed and reliability can be enhanced. The capacitance is reduced during reading. Consequently, a reading speed can be increased.
According to the tenth aspect of the present invention, a voltage applied when the depletion layer is generated and disappears in the ON and OFF states can be controlled by the charges generated on the gate insulation film by the dielectric. Consequently, more effects can be obtained by the depletion layer.
In order to solve the above-mentioned problems, it is an object of the present invention to add a function of changing a gate capacitance to a gate electrode so as to prevent a current driving capability from being lowered due to a drop in a supply voltage with scaling and to decrease a switching loss.
It is another object of the present invention to enhance chip performance by forming a depletion layer on the gate electrode to relieve an electric field of a gate insulation film when two or more kinds of supply voltages are used for one integrated circuit formed on the same chip.
It is a further object of the present invention to enhance performance of a capacitor which can change a capacitance and an effective thickness of a dielectric film to optimize characteristics of the capacitor depending on uses.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.